The present invention relates generally to semiconductor electronic circuits and, more particularly, to a system and method for evaluating gate oxide integrity for semiconductor microchips.
Gate oxide integrity (GOI) is a critical metric for the effective functioning of the transistor. With scaling of devices the gate oxides have become thinner to the extent that present day devices use oxides on the range 12–24 Angstroms. This makes them more susceptible to defects which are detrimental to eventual yield of the devices, Defects cause enhanced leakage and eventually premature (non-intrinsic) breakdown of oxides. The GOI integrity needs to be evaluated early in the device processing in the front end of the line to prevent unnecessary, wasteful utilization of time and resources in the back end of the line (BEOL). Present methods use an in-line invasive probe on a few sampled sites to determine current-voltage characteristics and from it to assess gate oxide quality or health.
Currently, there is not a good non-contact system or method to test gate oxide integrity during the semiconductor microchip manufacture itself. All existing methods use probes to test the gate oxide integrity after the semiconductor processing is completed (End of line). In addition, the probes or methods used in the current test systems can introduce contamination on the semiconductor wafers. Moreover, the testing systems only test a small set of specific sites on the semiconductor wafer. Thus they do not provide any wafer-spatial signature information. Active feedback of any spatial yield loss because of gate oxide integrity degradation is critical. Lack thereof results in continued faulty processing.
Therefore, what is needed, is a non-invasive system and method that tests gate oxide integrity, in-line amidst the different semiconductor processes. The method also needs to be fast, efficient, with more wafer spatial signature information, in order to provide active feedback and thus control process excursions and thus reduce yield loss.